The present invention relates in general to integrated circuits, and in particular to a power efficient and cost effective circuit for adjusting duty cycle of periodic signals.
In some circuits such as those used in communication systems, there is often a need for a reference signal with a tightly controlled duty cycle. For example, timing requirements such as transmission templates in communication systems do not permit reference signals having a duty cycle that deviates much from 50%. In telecommunication systems such as T1/E1 or T3/E3/STS1, however, a reference clock signal may be supplied from different sources resulting in a duty cycle that is not well controlled. To adjust the duty cycle of the reference clock in such systems, designers often use phase-locked loops (PLLs) or various types of pulse shaping filters. These types of timing adjustment circuitry that rely on feedback techniques or filtering, while effective in providing accurate control, tend to be more susceptible to noise, consume larger silicon area, and contribute appreciably to power dissipation. These drawbacks are exacerbated in applications involving multiple channels on the same silicon die wherein each channel requires a separate timing adjustment circuit and crosstalk between adjacent channels is a concern.
There is a need for duty cycle adjustment circuitry that is robust and efficient in terms of power consumption and circuit area.